Tabl Cynhwysion:
“...2 -- 2.1 Scalars and Array Literals -- 2.2 Names (Identifiers) -- 2.3 Object Declarations -- 2.4 Expressions -- 3: Sequential Statements -- 3.1 PROCESS Statement -- 3.2 Variable
Assignment Statement -- 3.3 Sequential Signal
Assignment Statement -- 3.4 IF Statement -- 3.5 CASE Statement -- 3.6 LOOP Statement -- 3.7 NEXT Statement -- 3.8 EXIT Statement -- 3.9 WAIT Statement -- 3.10 ASSERT Statement -- 3.11 Subprograms -- 4: Advanced Types -- 4.1 Extended Types -- 4.2 Composite Types — Arrays -- 4.3 Composite Types — Records -- 4.4 Alias Declaration -- 4.5 Predefined Types: Text and Lines -- 4.6 Access Types -- 5: Signals & Signal
Assignments -- 5.1 Structural Signals in Netlisting -- 5.2 Process Communication -- 5.3 Process/Component Connection — Testbench -- 5.4 Signal Declaration -- 5.5 Entity Signal Port Declarations -- 5.6 Signal
Assignment in a Process -- 5.7 Signal Delay -- 5.8 Sequential Signal
Assignment Hazards -- 5.9 Simulation Cycle -- 5.10 Simulation and WAIT Statements -- 5.11 Sensitivity List -- 6: Concurrent Statements -- 6.1 The Process -- 6.2 Concurrent Signal
Assignments -- 6.3 Conditional Signal
Assignments -- 6.4 Selected Signal
Assignments -- 6.5 Concurrent Procedure Call -- 6.6 BLOCK Statements -- 7: Structural VHDL -- 7.1 Component Instantiation Using Named Notation -- 7.2 Generate Statement -- 7.3 Hierarchy -- 7.4 Configurations -- 7.5 Generics -- 8: Packages & Libraries -- 8.1 Constant Declarations -- 8.2 Deferred Constants -- 8.3 Subprograms in Packages -- 8.4 Component Declarations -- 8.5 Selected Names -- 8.6 USE Statement -- 8.7 General Notes on Procedures in Packages -- 8.8 Typical Vendor Packages -- 8.9 IEEE Package 1164 -- 9: Advanced Topics: Adding Apples & Oranges -- 9.1 Overloading -- 9.2 Resolution Functions and Multiple Drivers -- 9.3 Symbolic Attributes -- 10: VHDL & Logic Synthesis -- 10.1 Synthesis-Ready Code -- 10.2 CASE Statement Synthesis -- 10.3 FOR Statement Synthesis -- 10.4 A 4-Bit Adder -- 10.5 Synthesis and the WAIT Statement -- 10.6 State Machines in VHDL -- 10.7 Predefined Attributes for Synthesis -- Reserved Words -- Application Examples -- B.1 Vending Drink Machine — Count Nickels -- B.2 Structural Description of a Design Entity -- B.3 Carry-Look-Ahead Adder -- VHDL Structure & Syntax -- C.1 Design Hierarchy -- Architectures -- Processes -- Subprograms -- Packages -- C.2 Concurrent Statements -- Block Statement -- Component Instantiation Statement -- Concurrent Assertion Statement -- Concurrent Procedure Call -- Concurrent Signal
Assignment Statement -- Generate Statement -- Process Statement -- C.3 Sequential Statements -- Assertion Statement -- Case Statement -- Exit Statement -- If Statement -- Loop Statement -- Next Statement -- Null Statement -- Procedure Call Statement -- Return Statement -- Signal
Assignment Statement -- Variable
Assignment Statement -- Wait Statement -- C.4 Specifications -- Attribute Specification -- Configuration Specification -- C.5 Library & USE Clauses -- LIBRARY Clause -- USE Clause -- C.6 Declarations -- Alias Declaration -- Attribute Declaration -- Component Declaration -- Constant Declaration -- File Declaration -- Signal Declarations -- Subprogram Declaration -- Subprogram Body -- Subtype Declaration -- Type Declaration -- Variable Declaration -- C.7 Library Units -- Architecture Body -- Configuration Declaration -- Entity Declaration -- Package Body -- Package Declaration -- C.8 Predefined Attributes -- Array-Related Attributes -- Signal Attributes -- Type-Related Attributes -- New Attributes in VHDL 92 -- C.9 Package STANDARD -- C.10 TEXTIO Package....”
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