Improving dependability with low power fault detection model for skinny-hash.

著者: Arvind Barge, Sonal¹ (AUTHOR), Mary, Gerardine Immaculate¹ (AUTHOR) gerardine@vit.ac.in

ソース: PLoS ONE. 12/19/2024, Vol. 19 Issue 12, p1-18. 18p.

件名: *COMPUTER hardware description languages, *INTERNET of things, *ALGORITHMS, *POPULARITY, *BLOCK ciphers

Design and FPGA implementation of AHB-to-APB bridge.

著者: Shanthi, G.¹ (AUTHOR) Shanthi_g@vnrvjiet.in, Sravani, K. Girija² (AUTHOR) Kondavitee.sravani@kluniversity.in, Vali, SK. Shoukath¹ (AUTHOR) shoukatvali_sk@vnrvjiet.in, Ashwini, Nangunuri¹ (AUTHOR) ashwininangunuri8135@gmail.com, Sainath, Gangaraboina¹ (AUTHOR) sainadharyaan786@gmail.com, sai, Pyata Gaurav¹ (AUTHOR) gaurava.2253@gmail.com

ソース: Microsystem Technologies. Apr2025, Vol. 31 Issue 4, p925-934. 10p.

件名: *COMPUTER hardware description languages, *INTERNET protocol address, *MODERN architecture, *SOFTWARE development tools, *BUSES, *SYSTEMS on a chip

Stability analysis of improved combined-mode power converter and power flow control using FPGA.

著者: Sathiyanathan, M¹ (AUTHOR) sathiyangm@gmail.com, Jaganathan, S² (AUTHOR)

ソース: International Journal of Electronics. Jun2024, Vol. 111 Issue 6, p989-1011. 23p.

件名: *INTEGRATED circuits, ELECTRICAL load, COMPUTER hardware description languages, GATE array circuits, SINE waves, FIELD programmable gate arrays, PULSE width modulation

Hardware architectures for computing the cosine transforms over the finite field F28$\mathbb {F}_{2^8}$.

著者: de Oliveira Neto, José R.¹ (AUTHOR) joserodrigues.oliveiraneto@ufpe.br, Coutinho, Vítor A.² (AUTHOR)

ソース: Electronics Letters (Wiley-Blackwell). Nov2024, Vol. 60 Issue 22, p1-3. 3p.

件名: FIELD programmable gate arrays, COMPUTER hardware description languages, COSINE transforms, FINITE fields, GATE array circuits

EXPLORING THE FEASIBILITY OF PARALLEL I²C SENSOR INTERFACING ON AN EDUCATIONAL FPGA BOARD: RESOURCE UTILIZATION ANALYSIS AND DESIGN CONSIDERATIONS.

著者: OPREA, Claudiu-Alexandru¹ (AUTHOR) Claudiu.Oprea@emd.utcluj.ro, KIREI, Botond Sándor² (AUTHOR) botond.kirei@bel.utcluj.ro, TURCU, Romulus Valeriu Flaviu³ (AUTHOR) flaviu.turcu@ubbcluj.ro

ソース: Studia Universitatis Babes-Bolyai, Physica. 2023, Vol. 68 Issue 1/2, p57-10. 10p.

件名: *COMPUTER hardware description languages, *LOGIC circuits, *COMPUTERS in education, *COMPUTER performance, *EDUCATIONAL objectives

Directed Test Generation for Hardware Validation: A Survey.

著者: Jayasena, Aruna¹ (AUTHOR) arunajayasena@ufl.edu, Mishra, Prabhat¹ (AUTHOR) prabhat@ufl.edu

ソース: ACM Computing Surveys. May2024, Vol. 56 Issue 5, p1-36. 36p.

件名: *PUBLIC key cryptography, GRAPH neural networks, COMPUTER hardware description languages, SINGLE event effects, SYMMETRIC-key algorithms, DEBUGGING

Languages, design methods, and tools for electronic system design : selected contributions from FDL 2018 / Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große, editors.

出版種別: Book

件名: Formal methods (Computer science) -- Congresses, Software engineering -- Congresses, Computer software -- Verification -- Congresses, Software architecture -- Congresses, Computer hardware description languages -- Congresses, Computer hardware description languages, Computer software -- Verification, Formal methods (Computer science), Software architecture, Software engineering, proceedings (reports), Conference papers and proceedings, Actes de congrès

その他の著者: Kaźmierski, Thomas J.

その他の著者: Steinhorst, Sebastian

その他の著者: Grosse, Daniel

Other Titles: FDL 2018.

オンライン･アクセス: https://holycross.idm.oclc.org/login?auth=cas&url=https://link.springer.com/10.1007/978-3-030-31585-6

Introduzione al Progetto di Sistemi Digitali / Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita.

著者: Donzellini, Giuliano, author

出版種別: Book

件名: Computer hardware description languages, Logic circuits, System design

その他の著者: Oneto, Luca, author

その他の著者: Ponta, Domenico, author

その他の著者: Anguita, Davide, author

オンライン･アクセス: https://holycross.idm.oclc.org/login?auth=cas&url=https://link.springer.com/10.1007/978-88-470-4026-7

Hardware efficient reconfigurable digital down converter for software radio receiver.

著者: Datta, Debarshi¹ (AUTHOR) debarshidatta7@gmail.com, Dutta, Himadri Sekhar^1,2 (AUTHOR)

ソース: International Journal of Electronics Letters. Jun2024, Vol. 12 Issue 2, p107-118. 12p.

件名: *SOFTWARE radio, *COMPUTER hardware description languages, *FINITE impulse response filters, *PROCESS capability, *GATE array circuits, *SUCCESSIVE approximation analog-to-digital converters

The Ubimus Plugging Framework: Deploying FPGA-Based Prototypes for Ubiquitous Music Hardware Design.

著者: Keller, Damián, Jagwani, Aman, Lazzarini, Victor

ソース: Computers (2073-431X); Apr2025, Vol. 14 Issue 4, p155, 24p

件名: COMPUTER hardware description languages, LEARNING curve, GATE array circuits, LOGIC circuits, INTEGRATED circuits

TRANSACTION-LEVEL DESIGNING OF NEUROMORPHIC PROCESSORS MICROARCHITECTURE.

著者: Lukashov, Ivan¹, Antonov, Alexander¹

ソース: Proceedings of the International Multidisciplinary Scientific GeoConference SGEM. 2024, Vol. 24, p81-88. 8p.

件名: *ARTIFICIAL neural networks, *COMPUTER hardware description languages, *SOFTWARE libraries (Computer programming), *RAPID prototyping, *COMMUNICATION barriers

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs.

著者: González, César¹ (AUTHOR) mariano.ruiz@upm.es, Ruiz, Mariano¹ (AUTHOR) antonio.cruiz@upm.es, Carpeño, Antonio¹ (AUTHOR) a.pinas@upm.es, Piñas, Alejandro¹ (AUTHOR), Cano-Ott, Daniel² (AUTHOR) daniel.cano@ciemat.es, Plaza, Julio² (AUTHOR) julio.plaza@ciemat.es, Martinez, Trino² (AUTHOR) trino.martinez@ciemat.es, Villamarin, David² (AUTHOR) david.villamarin@ciemat.es

ソース: Sensors (14248220). May2024, Vol. 24 Issue 9, p2724. 14p.

件名: *FINITE impulse response filters, *COMPUTER hardware description languages, *LIQUID scintillators, *NEUTRON counters, *NUCLEAR physics, *FAST neutrons, *SUCCESSIVE approximation analog-to-digital converters, *ENERGY function, *ANALOG-to-digital converters

Fine grain algorithm parallelization on a hybrid control-flow and dataflow processor.

著者: Korolija, Nenad

ソース: Journal of Big Data; 2/22/2025, Vol. 12 Issue 1, p1-25, 25p

件名: COMPUTER hardware description languages, TIME management, SCALABILITY, ALGORITHMS, EXPERTISE

Easy and Straightforward FPGA Implementation of Model Predictive Control Using HDL Coder.

著者: Purraji, Marziye, Zamiri, Elyas, de Castro, Angel

ソース: Electronics (2079-9292); Feb2025, Vol. 14 Issue 3, p419, 27p

件名: COMPUTER hardware description languages, LOGIC circuits, CONVERTERS (Electronics), COMPUTER performance, PREDICTION models

Design and Experimental Validation Of FPGA Based Digital Control Scheme Of The Nearest Level Modulation Method For Modular Multilevel Converter Topology.

Alternate Title: Modüler Çok Seviyeli Dönüştürücü Topolojisi İçin En Yakın Seviye Modülasyon Yönteminin FPGA Tabanlı Dijital Kontrol Şemasının Tasarımı ve Deneysel Doğrulaması. (Turkish)

著者: KURTOĞLU, Mehmet, EROĞLU, Fatih, VURAL, Ahmet Mete

ソース: Firat University Journal of Experimental & Computational Engineering (FUJECE); Feb2025, Vol. 4 Issue 1, p44-58, 15p

件名: COMPUTER hardware description languages, INTEGRATED circuits, RESEARCH personnel, VOLTAGE control, TOPOLOGY, CASCADE converters

DEVS-Based CDC Synchronizer Design for Fast Debugging of Metastability.

著者: Kwon, Bo Seung, Han, Young Shin, Lee, Jong Sik

ソース: Electronics (2079-9292); Dec2024, Vol. 13 Issue 24, p5048, 18p

件名: COMPUTER hardware description languages, DISCRETE systems, SYSTEMS on a chip, SETUP time, TIME management, DIGITAL electronics

Design of decryption process for advanced encryption standard algorithm in system-on-chip.

著者: Prathap, Joseph Anthony, Raj, Mrinal, Patnaik, Ritu

ソース: International Journal of Electrical & Computer Engineering (2088-8708); Dec2024, Vol. 14 Issue 6, p6838-6845, 8p

件名: ADVANCED Encryption Standard, COMPUTER hardware description languages, INTEGRATED circuit layout, ELECTRONIC design automation, GATE array circuits

Free Software Support for Compact Modelling with Verilog-A.

Alternate Title: Odprtokodna programska oprema za uporabo kompaktnih modelov v jeziku Verilog-A. (Slovenian)

著者: Bűrmen, Árpád, Tuma, Tadej, Fajfar, Iztok, Rojec, Janez Puhan,Žiga, Kunaver, Matevž, Tomažič, Sašo

ソース: Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials; Dec2024, Vol. 54 Issue 4, p271-281, 11p

件名: COMPUTER hardware description languages, FREEWARE (Computer software), ANALOG circuits, SEMICONDUCTOR devices

xyz Modelo de Optimización de Arreglos de Cometas Captadoras de Energías Sostenibles.

Alternate Title: xyz Model Applied to Kites Collector Arrays of Sustainable Energy.
Modelo de Otimização de Arranjos de Generador Eólico para Captação de Energia Sustentável.

著者: Sandoval-Ruiz, Cecilia E.¹ cesandova@gmail.com

ソース: Revista Técnica de la Facultad de Ingeniería de la Universidad del Zulia. 2024, Vol. 47, p1-16. 16p.

件名: *COMPUTER hardware description languages, *SHIFT registers, *WIND power, *ADAPTIVE filters, *ENERGY industries

Implementación en FPGA de la Calibración de un Sistema de Antenas Inteligentes con Superresolución en la Estimación de DOA.

Alternate Title: Smart Antennas System FPGA Calibration Implementation with Super Resolution DOA Estimation.

著者: Guerra, Yunior Ibarra¹ yuniorig2016@hotmail.com, Ramírez, Noslen Rojas¹ noslenrr71@outlook.com, Ramírez Zaldivar, Alexander R.¹ alex.r_92@outlook.com, Violat, Abel Hernández¹ abelhviolat@outlook.com

ソース: Ingeniería Electrónica. Automatica y Comunicaciones. 2024, Vol. 45 Issue 1, p1-15. 15p.

件名: *ADAPTIVE antennas, *COMPUTER hardware description languages, *PDS (Computer system), *FIELD programmable gate arrays, *DIRECTION of arrival estimation, *PROBLEM solving, *CALIBRATION