Improving dependability with low power fault detection model for skinny-hash.

Autori: Arvind Barge, Sonal¹ (AUTHOR), Mary, Gerardine Immaculate¹ (AUTHOR) gerardine@vit.ac.in

Fonte: PLoS ONE. 12/19/2024, Vol. 19 Issue 12, p1-18. 18p.

Soggetti: *COMPUTER hardware description languages, *INTERNET of things, *ALGORITHMS, *POPULARITY, *BLOCK ciphers

40 The Role of Control-Structure Interaction in Deployable Autonomous Control Systems

Fonte: Dynamics of Civil Structures, Volume 2. May 09, 2025

A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation.

Autori: Rajasekaran, Arun Sekar¹ (AUTHOR), Azees, M.² (AUTHOR) azeesmm@gmail.com

Fonte: International Journal of Information Security. Feb2024, Vol. 23 Issue 1, p1-13. 13p.

Soggetti: *BODY area networks, *VERILOG (Computer hardware description language), *FIELD programmable gate arrays, *COMPUTER hardware description languages, *PRIVACY

Hardware-accelerated neural network model for early prediction of sudden cardiac arrest based on heart rate variability metrics.

Autori: Pan, Sheng-Yueh¹ (AUTHOR) jason1019.ece09g@nctu.edu.tw, Nguyen, Duc Huy¹ (AUTHOR) ndhuyvn199@gmail.com, Chao, Paul C.-P.¹ (AUTHOR) pchao@nycu.edu.tw

Fonte: Microsystem Technologies. May2025, Vol. 31 Issue 5, p1231-1245. 15p.

Soggetti: *ARTIFICIAL neural networks, *VERILOG (Computer hardware description language), *MEDICAL sciences, *HEART beat, *CORONARY circulation

Design and FPGA implementation of AHB-to-APB bridge.

Autori: Shanthi, G.¹ (AUTHOR) Shanthi_g@vnrvjiet.in, Sravani, K. Girija² (AUTHOR) Kondavitee.sravani@kluniversity.in, Vali, SK. Shoukath¹ (AUTHOR) shoukatvali_sk@vnrvjiet.in, Ashwini, Nangunuri¹ (AUTHOR) ashwininangunuri8135@gmail.com, Sainath, Gangaraboina¹ (AUTHOR) sainadharyaan786@gmail.com, sai, Pyata Gaurav¹ (AUTHOR) gaurava.2253@gmail.com

Fonte: Microsystem Technologies. Apr2025, Vol. 31 Issue 4, p925-934. 10p.

Soggetti: *COMPUTER hardware description languages, *INTERNET protocol address, *MODERN architecture, *SOFTWARE development tools, *BUSES, *SYSTEMS on a chip

Reduction of Interference Terms in Wigner Ville Distribution using Machine Learning.

Autori: Satyanarayana, S. V. V.¹ (AUTHOR) svvsatyanarayana8589@gmail.com, Murali Krishna, B.¹ (AUTHOR) murali.ece713@gmail.com, Satyanarayana, P. V. V.¹ (AUTHOR) pvv.bunni@gmail.com, Kusuma Kumari, E.¹ (AUTHOR) kusuma.madhu.ece@gmail.com

Fonte: Circuits, Systems & Signal Processing. Mar2025, Vol. 44 Issue 3, p2041-2072. 32p.

Soggetti: *VERILOG (Computer hardware description language), *FIELD programmable gate arrays, *WIGNER distribution, *POWER density, *MACHINE learning

Improved Verilog‐A Based Artificial Neural Network Modeling Applied to GaN HEMTs.

Autori: Jarndal, Anwar¹ (AUTHOR) ajarndal@sharjah.ac.ae, Ansari, Md Hasnain² (AUTHOR), Dautov, Kassen³ (AUTHOR), Almajali, Eqab¹ (AUTHOR), Chauhan, Yogesh Singh² (AUTHOR), Majzoub, Sohaib¹ (AUTHOR), Mahmoud, Soliman A.¹ (AUTHOR), Bonny, Talal⁴ (AUTHOR)

Fonte: Advanced Theory & Simulations. Feb2025, Vol. 8 Issue 2, p1-11. 11p.

Soggetti: *VERILOG (Computer hardware description language), *ARTIFICIAL neural networks, *GALLIUM nitride, *COMPUTER simulation, *NONLINEAR statistical models, *NONLINEAR regression, *ELECTRIC conductivity

Implementation of Serial Peripheral Interface Slave Device Based on Uncommitted Logic Arrays.

Autori: Sinyukin, Alexander¹ sinyukin@sfedu.ru, Denisenko, Mark¹ dema@sfedu.ru, Isaeva, Alina¹ isaevaas@sfedu.ru, Kots, Ivan¹ inkots@sfedu.ru, Kovalev, Andrey² avkovalev@sfedu.ru

Fonte: Serbian Journal of Electrical Engineering. Feb2025, Vol. 22 Issue 1, p1-16. 16p.

Soggetti: *VERILOG (Computer hardware description language), *PROGRAMMABLE logic devices, *LOGIC circuits, *DIGITAL technology, *INTEGRATED circuits

FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder.

Autori: Elsayed, Ghada¹ (AUTHOR) Ghadakdr@gmail.com, Abass, Eman S.² (AUTHOR)

Fonte: Bulletin of the National Research Centre. 12/23/2024, Vol. 48 Issue 1, p1-16. 16p.

Soggetti: *VERILOG (Computer hardware description language), *RSA algorithm, *ELLIPTIC curves, *COPROCESSORS, *MULTIPLICATION

Modeling and application research of absolute gravimeter driven by a V-shaped linear ultrasonic motor.

Autori: Zhou, Lifeng^1,2 (AUTHOR) 310233897@qq.com, Xu, Hao³ (AUTHOR), Geng, Ranran^1,2 (AUTHOR), Yao, Zhiyuan³ (AUTHOR)

Fonte: Review of Scientific Instruments. Dec2024, Vol. 95 Issue 12, p1-12. 12p.

Soggetti: *VERILOG (Computer hardware description language), *FIELD programmable gate arrays, *ULTRASONIC motors, *STRUCTURAL dynamics, *PID controllers

Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL.

Autori: de Castro, Manuel¹ (AUTHOR), Osorio, Roberto R.² (AUTHOR), Vilariño, David L.³ (AUTHOR), Gonzalez-Escribano, Arturo¹ (AUTHOR), Llanos, Diego R.¹ (AUTHOR) diego@infor.uva.es

Fonte: Journal of Supercomputing. Jun2023, Vol. 79 Issue 9, p9866-9888. 23p.

Soggetti: *VERILOG (Computer hardware description language), *MULTIPLE comparisons (Statistics), *ALGORITHMS

Stability analysis of improved combined-mode power converter and power flow control using FPGA.

Autori: Sathiyanathan, M¹ (AUTHOR) sathiyangm@gmail.com, Jaganathan, S² (AUTHOR)

Fonte: International Journal of Electronics. Jun2024, Vol. 111 Issue 6, p989-1011. 23p.

Soggetti: *INTEGRATED circuits, ELECTRICAL load, COMPUTER hardware description languages, GATE array circuits, SINE waves, FIELD programmable gate arrays, PULSE width modulation

Hardware architectures for computing the cosine transforms over the finite field F28$\mathbb {F}_{2^8}$.

Autori: de Oliveira Neto, José R.¹ (AUTHOR) joserodrigues.oliveiraneto@ufpe.br, Coutinho, Vítor A.² (AUTHOR)

Fonte: Electronics Letters (Wiley-Blackwell). Nov2024, Vol. 60 Issue 22, p1-3. 3p.

Soggetti: FIELD programmable gate arrays, COMPUTER hardware description languages, COSINE transforms, FINITE fields, GATE array circuits

Generic FPGA Pre-Processing Image Library for Industrial Vision Systems.

Autori: Ferreira, Diogo^1,2 (AUTHOR) diogo.ferreira@introsys.eu, Moutinho, Filipe^2,3 (AUTHOR) joao.matos.carvalho@ulusofona.pt, Matos-Carvalho, João P.^3,4 (AUTHOR), Guedes, Magno¹ (AUTHOR) pedro.deusdado@introsys.eu, Deusdado, Pedro¹ (AUTHOR)

Fonte: Sensors (14248220). Sep2024, Vol. 24 Issue 18, p6101. 17p.

Soggetti: *VHDL (Computer hardware description language), *INDUSTRIALISM, *COMPUTER vision, *GATE array circuits, *IMAGE processing

Implementation of NonLinear Controller with Anti-Windup on Xilinx FPGA.

Autori: Ahmed, Samet¹ a.Samet@univ-soukahras.dz, Yahia, Kourd¹, Dimitri, Lefebvre²

Fonte: Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Sep2024, Vol. 49 Issue 9, p13005-13024. 20p.

Soggetti: *VHDL (Computer hardware description language), *PARTICLE swarm optimization, *FUZZY algorithms, *MEMBERSHIP functions (Fuzzy logic), *FUZZY logic, *ADAPTIVE fuzzy control

EXPLORING THE FEASIBILITY OF PARALLEL I²C SENSOR INTERFACING ON AN EDUCATIONAL FPGA BOARD: RESOURCE UTILIZATION ANALYSIS AND DESIGN CONSIDERATIONS.

Autori: OPREA, Claudiu-Alexandru¹ (AUTHOR) Claudiu.Oprea@emd.utcluj.ro, KIREI, Botond Sándor² (AUTHOR) botond.kirei@bel.utcluj.ro, TURCU, Romulus Valeriu Flaviu³ (AUTHOR) flaviu.turcu@ubbcluj.ro

Fonte: Studia Universitatis Babes-Bolyai, Physica. 2023, Vol. 68 Issue 1/2, p57-10. 10p.

Soggetti: *COMPUTER hardware description languages, *LOGIC circuits, *COMPUTERS in education, *COMPUTER performance, *EDUCATIONAL objectives

Directed Test Generation for Hardware Validation: A Survey.

Autori: Jayasena, Aruna¹ (AUTHOR) arunajayasena@ufl.edu, Mishra, Prabhat¹ (AUTHOR) prabhat@ufl.edu

Fonte: ACM Computing Surveys. May2024, Vol. 56 Issue 5, p1-36. 36p.

Soggetti: *PUBLIC key cryptography, GRAPH neural networks, COMPUTER hardware description languages, SINGLE event effects, SYMMETRIC-key algorithms, DEBUGGING

Languages, design methods, and tools for electronic system design : selected contributions from FDL 2018 / Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große, editors.

Tipo di pubblicazione: Book

Soggetti: Formal methods (Computer science) -- Congresses, Software engineering -- Congresses, Computer software -- Verification -- Congresses, Software architecture -- Congresses, Computer hardware description languages -- Congresses, Computer hardware description languages, Computer software -- Verification, Formal methods (Computer science), Software architecture, Software engineering, proceedings (reports), Conference papers and proceedings, Actes de congrès

Altri autori: Kaźmierski, Thomas J.

Altri autori: Steinhorst, Sebastian

Altri autori: Grosse, Daniel

Other Titles: FDL 2018.

Accesso online: https://holycross.idm.oclc.org/login?auth=cas&url=https://link.springer.com/10.1007/978-3-030-31585-6

Tools and Algorithms for the Construction and Analysis of Systems

Nomi associati: Gurfinkel, Arie, Heule, Marijn

Soggetti: TACAS, formal verification, software systems, hardware systems, static analysis, probabilistic programming, program synthesis, oncurrency, testing, simulations, verification of machine, Mathematical theory of computation, Computer hardware, Network hardware, Computer modelling and simulation, Software Engineering

Descrizione del file: application/pdf

Relation: Lecture Notes in Computer Science

URL di accesso: https://library.oapen.org/handle/20.500.12657/101664

Fundamental Approaches to Software Engineering

Nomi associati: Boronat, Artur, Fraser, Gordon

Soggetti: software engineering, requirements, design, architecture, modeling, applications of AI to software engineering, software engineering of AI-based syste,s, software quality, model-driven engineering, processes, software evoluation, Software Engineering, Operating systems, Mathematical theory of computation, Computer hardware, Systems analysis and design, Natural language and machine translation

Descrizione del file: application/pdf

Relation: Lecture Notes in Computer Science

URL di accesso: https://library.oapen.org/handle/20.500.12657/101665